(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more Particularly to processes related to etching of organic, low dielectric constant insulative layers on semiconductor wafers.
(2) Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. The wiring layers are formed by first depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer which is patterned and etched to form wiring interconnections between the device contacts thereby creating a first level of basic circuitry. These basic circuits are then further interconnected by utilizing additional wiring levels laid out over a additional insulating layers with via pass throughs.
The performance or speed of the integrated circuits is determined in large part by the conductance and capacitance of the metal wiring network. For many years aluminum wring and silicon oxide inter level dielectric layers have been the norm. As device densities increase and geometries decrease, however, the RC time constraints of the interconnective wiring have become increasingly restrictive to integrated circuit performance. Thus in order to further improve performance, researchers have, in recent years, intensified their search for a metallurgy offering greater conductivity and insulative materials with lower dielectric constants. Copper is a prominent replacement for aluminum while various organic insulators such as parylene, and arylene ether polymers, have been successfully used as low dielectric constant(low-k) replacements for silicon oxide. Porous silica based materials such as siloxanes, aerogels and xerogels have also been implemented as ILD(inter layer dielectric) and IMD(inter-metal dielectric) layers. Fluorinated polyimides offer some improvement in dielectric constant lowering over conventional polyimides.
Many of the low-k dielectric materials, in particular the arylene ether based polymers, for example FLARE.TM. (FLuorinated ARylene Ether provided by Allied Signal Inc., 101 Columbia Road, P.O. Box 4000, Morristown, N.J. 07962) and PAE II.TM. or Lo-K.TM. 2000 (Poly Arylene Ether provided by the Schumacher Chemical Company which is a unit of Air Products and Chemicals, Inc., 7201 Hamilton Boulevard, Allentown, Pa. 18195-1501), exhibit patterning problems because of their low etch rate selectivities with respect to photoresist.
FLARE, PAE II, and other arylene ether polymer dielectric layer materials require an oxygen based etchant chemistry for effective patterning to form contact or via openings. Etching is done by RIE(reactive ion etching) or by plasma etching. Typically an O.sub.2 /Ar or O.sub.2 /He etchant chemistry is used. White, L. K., U.S. Pat. No. 4,470,871 utilizes a pure oxygen plasma to etch polyimide layers which have received a prior surface hardening treatment in a fluorine containing plasma.
In order to (contend with the poor etch rate selectivity of these organic low-k materials, a hardmask is used to etch the polymer layer. A layer of silicon oxide, deposited, by PECVD(plasma enhanced chemical vapor deposition) is applied over the cured polymer layer. A silicon dioxide hardmask is formed by patterning the silicon oxide layer. The SiO.sub.2 hardmask can then be used to pattern the polymer dielectric layer. Havermann, R. H., U.S. Pat. No. 5,482,894 uses an oxygen plasma in a an HDP(high density plasma) etching tool to etch contact openings in an organic dielectric layer using an oxygen plasma and a photoresist patterned inorganic cap layer over the organic layer.
Although the O.sub.2 /Ar or O.sub.2 /He etchant chemistry is an effective etchant for the polymer layer, problems with respect to the profile of the openings etched in the polymer layer and the etching behavior of the hardmask are encountered. Under some etchant conditions severe bowing of the via profile is produced. Such a profile is shown in FIG. 1a. The polymer layer 12 is deposited over a patterned metal layer which is coated with a TiN ARC(anti reflective coating) 10. The via opening 16 patterned by the hardmask 14, has bowed sidewalls 18. Under the etching conditions which lead to the bowed profile, the hardmask profile remains essentially vertical. By varying the etching conditions to reduce the bowing of openings in the polymer, the hardmask begins to exhibit an angular aspect similar to faceting. This is shown in the cross section of FIG. 1b where a contact/via opening 16 in the polymer layer 12 is essentially vertical but the hardmask 14 has developed a severe angular aspect or facet 19 which has been caused by ion bombardment.
Faceting of the hardmask causes problems in maintaining pattern integrity as well as inadequate metal removal problems during a subsequent tungsten CMP(chemical mechanical polishing) process step. The bowing phenomenon and the hardmask faceting phenomenon work against each other. Thus as the polymer profile bowing is reduced the hardmask faceting increases. It is clear that the simple O.sub.2 /Ar chemistry is inadequate for forming precision vias in polymer dielectric interlayers, in particular in sub-quarter micron technologies.
Jeng, S., U.S. Pat. No. 5,486,493 and U.S. Pat. No. 5,591,677 show methods of using low-k organic dielectric materials to form multilevel interconnects. Silicon oxide layers are used as hardmasks for patterning the organic layers and are cited, not only to overcome the etchant selectivity problems, but also to reduce subsequent hillock/void formation of metal lines, improve heat dissipation, and to serve as a barrier against mechanical instability of the organic polymer. However, etchant chemistries for the organic polymers are not given.